NEW DELHI — In a significant milestone for India’s domestic semiconductor ecosystem, 175 student-designed chips have been successfully taped out at the Semiconductor Laboratory in Mohali under its 180-nanometre technology node, alongside 79 student designs processed at overseas foundries. Responding to parliamentary queries raised by Congress Member of Parliament Manish Tewari, Minister of State for Electronics and Information Technology Jitin Prasada informed the Lok Sabha that government-backed capacity-building programs have now trained over 68,000 students in end-to-end chip design. Taping out represents the final phase of integrated circuit design where digital blueprints are dispatched to manufacturing foundries for physical silicon fabrication.
Beyond academic achievements, 25 semiconductor designs created by Indian startups and micro, small, and medium enterprises have been successfully taped out across various global foundries. These domestic enterprise projects include fabrication at advanced technology nodes such as the 12-nanometre process at Taiwan Semiconductor Manufacturing Company. The initiatives have been executed under the Design Linked Incentive scheme, which approved 24 commercial projects between mid-2023 and 2025 to develop specialized chips for critical sectors including video surveillance, drone detection, microprocessors, satellite communications, LED drivers, and Internet of Things systems.
The Union government highlighted that beneficiary startups under the Design Linked Incentive scheme have attracted venture capital investments exceeding four times the financial assistance disbursed by the state, reflecting robust investor confidence in domestic technological capabilities. India currently accounts for approximately 20 per cent of the world’s semiconductor design engineers, housing over 1.25 lakh design professionals and hosting 7 per cent of global semiconductor Global Capability Centres. Officials emphasized that these academic and commercial milestones demonstrate steady progress under the Chips to Startup Programme and Design Linked Incentive Scheme toward achieving long-term self-reliance in semiconductor manufacturing and design.
